A conventional Liquid Crystal Display (LCD) generally has a refresh rate of more than 60 Hz (that is, more than 60 frames are refreshed per second) so as to meet the display requirement of moving pictures. A higher refresh rate means that the drive circuit has to provide a drive signal of a higher frequency for the pixel unit of the LCD panel. To maintain a valid high frequency driving, a higher drive voltage is needed in the circuit. However, using a drive signal of both high frequency and high voltage for a long term will not only damage the devices but also consume much power, which is not conducive to energy saving and environmental protection.
For the purpose of realizing low-voltage drive, a technology in which the drive frequency is adjusted depending on the picture to be displayed is proposed in conventional technologies. For example, when display moving pictures, a normal frequency higher than 60 Hz is used for driving; while the drive frequency is accordingly decreased when display stationary pictures. The above driving solution may be realized by modifying the drive circuit. However, in real applications, the low frequency and low voltage will make the Voltage Holding Ratio (VHR) of the pixel unit (which is amplitude decreasing ratio of the time-variant voltage after the pixel unit is charged) low, thereby deteriorating the screen flicker.
A general formula for calculating VHR is as follows:
  VHR  =      100    ⁢    %    ×          (              1        -                                            I              leak                        ×                          t              frame                                                          C              st                        +                          C              LC                                          )      
where Ileak is the leakage current of the circuit, tframe is time for displaying a frame, Cst is storage capacitance of the pixel electrode, CLC is the liquid crystal capacitance. When the refresh rate is changed, tframe is the first to change. For example, under a refresh rate of 60 Hz, tframe is 16.7 ms. When the refresh rate is reduced to 30 Hz, tframe will be 33.4 ms. It is thus seen that (Cst+CLC) has to be adjusted dynamically in order to maintain VHR.
As illustrated in FIG. 1, a configuration which dynamically adjusts the storage capacitance Cst is employed in the conventional arts. A TFT 101 is the driving TFT; a parasitic capacitor Cst1 is formed between the common electrode line 103 and the pixel electrode 105. When displaying a stationary picture, the drive frequency of the LCD is decreased, and a dedicated TFT 102 in a regular pixel is driven, that is, the TFT 102 is turned on. As a result, the electrode 104 is connected to the common electrode line 103, thereby increasing the area of the pixel electrode for generating the parasitic capacitor, and the parasitic capacitor Cst2 is formed between the electrode 104 and the pixel electrode 105, which in turn increases the parasitic capacitor Cst=Cst1+Cst2 and maintains VHR at a high level. However, in the above application of the conventional art, the TFT 102 for controlling the variable Cst has to be introduced in the circuit and signal lines dedicated for the TFT 102 have to be provided, in order to achieve the adjustment of the magnitude of the parasitic capacitor depending on the frequency. Introducing those elements in the pixel region will definitely affect the transmissivity of the backlight, thereby reducing the aperture ratio of the panel and impacting the display quality.